A Study of Floorplanning Challenges and Analysis of macro placement approaches in Physical Aware Synthesis

نویسنده

  • Shivani Garg
چکیده

The macro placement is a governing factor in design flow in terms of timing criticality and congestion metrics. Also tape-out schedules are affected because of quality of macro placement or floorplanning. As hierarchical approach is followed for design closure today, there are multiple macro iterations back and forth between synthesis and implementation tool until the design meet all timing and design constraints. Traditional flow takes much time to figure out the best floorplan in terms of timing, Quality of results (QoR) and congestion. Now, physical aware synthesis gives a user an opportunity to cut the implementation time at later stages. The approach used here is RTL level floorplanning to enhance the quality of floorplan and also save multiple iterations. In one shot we get automatic floorplan initially generated by tool and then used by Place and Route (P&R) team for further processing. Also a rough estimate of wire delays and routes to calculate parasitic value, hence delays is obtained. There are multiple ways of placing macros in a floorplan which varies with shape of die and core utilization of design. So when multi macro placement approaches are applied simultaneously, then one can choose the best floorplan in terms of QoR and design metrics and then take it to implementation tool. After studying floorplan and macro placement challenges, there is a need to reduce cycle time between synthesis and implementation tool. In this work, different macro placement approaches are applied on design for different shapes of die (rectangular and rectilinear) using various parameters and then analyzed the timing, design metrics and congestion of various approaches. The results obtained show that every macro placement approach has different effect for different types of die on timing, congestion and power. Thus we can easily automate floorplanning for different shapes of die and reduce cycle time from months to few weeks. As checked on a design with 500k instances and 18 macros, with utilization of 59% if rectangular die is chosen the approach 3rd gives best result in congestion of 0.1% and the cycle time reduced from weeks to days.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a tim...

متن کامل

Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics

On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become increasingly more difficult and ineffective as multiprocessor complexity increases. Compared with traditional ASIC architectures, multiprocessors have homogeneous processing elements and regular network topologies. Theref...

متن کامل

Thermal-Aware Physical Design Flow for 3-D ICs

3-D IC technologies have recently drawn great interest due to their potential performance improvement, power consumption reduction and heterogeneous components integration. One of the largest challenges in 3-D IC design is heat dissipation. In this paper we propose a thermal-aware physical design process for 3-D ICs, including floorplanning (3DFP-T), placement (T3Place) and routing (TMARS). Tem...

متن کامل

Leveraging Physically Aware Design-for-Test to Improve Area, Power, and Timing

Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i...

متن کامل

On-chip implementation of multiprocessor networks and switch fabrics

On-chip implementationofmultiprocessor systemsneeds toplanarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular. Therefore, traditional ASIC floorplanning methodologies that perform macro placement are not suitable for MPSoC de...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2016